Breaking #AI #Stock News: GBT (OTCPK:
$GTCH) Segmental Update: Magic2, a Suite of Eight AI Driven #EDATools Assisting
Engineers with Faster #Semiconductor Design; @gbtt_inc #artificialintelligence
Santa Monica, CA,
June, 13 2023 –
(Investorideas.com Newswire) GBT Technologies Inc. (OTC PINK:
GTCH) (“GBT” or the “Company”), is pleased
to provide an update covering its EDA segment intellectual properties (“IP”)
portfolio.
Read this news,
feat5uring GTCH in full at https://www.investorideas.com/CO/GOPH/news/2023/06131Magic2.asp
Magic2
(internal project name), is an AI driven electronic design automation (EDA) software
Suite helping engineers to speed up time consuming task work during the integrated
circuits (IC) design phase. This week GBT received patent approval for its
Epsilon tool which means that four out of the eight tools received patent
approval. Magic2 consists of eight integrated software applications that each
cover specific component processes of the IC design cycle.
The
tools complement each other and will help drastically reduce the development
costs and speed up the IC design development cycle.
§ Epsilon - RV
(Reliability Verification) Software for real-time analysis and Auto-Correct of integrated
Circuits Reliability issues, among them are EM (Electromigration), SH
(Self-Heat), IR Drop [1], and another RV phenomenon [2]. Notice of Allowance issued – Functioning
Software Demo available,
§ Omega – Automatic Design Rule Correction
Software of physical IC layout block. The program reads a process rule deck, a
GDSII [3], Oasis data [4] and automatically fixes all DRC [6] violations,
maintaining hierarchy and LVS, RV, DFM [7] compliance. Notice of Allowance issued,
- Sigma -
LVS [5] Automatic Correction of IC Layout Blocks. The program reads an LVS
Deck and a GDSII, Oasis data and based on schematic fixes the physical
layout. The program will re-wire nets, maintaining DRC, RV, and DFM
correctness. – Patent
issued.
§ Phi
- Automatic IP layout blocks generator to create
from scratch IC layout blocks (For example: A USB unit, or a MEMORY unit),
based on hardware description language or a circuit’s schematic. The system
reads the circuit’s schematic or HDL [8] and automatically generates the
block in a given process (for example: 5nm). The generated block is LVS, DRC,
RV and DFM compliant. –Notice of Allowance issued.
- Tau - Patent
and information pending. *
- Delta
- Patent and information pending. *
- Kappa
- Patent
and information pending.
*
§ Zeta - Patent and information pending. *
“It
sounds technical because it is, but simply spoken, Magic2** is a suite of
individual EDA tools which we believe can potentially save 1000’s and 1000’s
hours of engineering time, speeding up the microchip design process and at the
same time building better, faster, greener, cheaper, and more reliable
microchips. Epsilon has been a double milestone for GBT Technologies Inc. as we
already developed a limited working software version V1.0 which has performed
in an operational setting and started the whole Magic2 concept. With all the positive
industry feedback, GBT will continue to focus on expanding the family of its
various EDA patents and concentrating on strategic potential partnerships with
the goal of integrating these technologies into a broad marketplace, diversifying
the risk within all these areas, and increasing shareholder value of that
portfolio” said Mansour Khatib, CEO of GBT.
Company
is starting a limited video series “GBT News from the CEO Corner” on the
company blog where the CEO will share more insight and short video clips about
ongoing news, and patents, in order to provide more transparency and provide easier
understanding of the technology to shareholders. The first video will be
published by the end of the month. https://gbtti.com/blog/.
There is no
guarantee that the Company will be successful in researching, developing, or
implementing this system. In order to successfully implement this concept, the
Company will need to raise adequate capital to support its research and, if
successfully researched and fully developed, the Company would need to enter
into a strategic relationship with a third party that has experience in manufacturing,
selling, and distributing this product. There is no guarantee that the Company
will be successful in any or all of these critical steps.
[1]
- IR drop, also known as voltage drop, refers to the phenomenon where there is
a drop in voltage across a conductor or a power distribution network due to the
resistance of the conductor itself. When current flows through a conductor, it
encounters resistance, and according to Ohm's Law (V = I * R), a voltage drop
occurs across the resistance.
[2]
– RV: Reliability Verification - IC reliability verification refers to the
process of assessing and ensuring the reliability of integrated circuits
throughout their lifecycle. It involves identifying potential failure
mechanisms, analyzing the effects of stress factors (such as temperature,
voltage, aging, and others), and verifying that the IC meets specified
reliability requirements.
[3]
- GDSII (Graphic Data System II) is a file format commonly used in the
semiconductor industry to describe the physical layout of integrated circuits
(ICs) at the mask level. It is a binary file format that represents the
geometric shapes, layers, and connectivity of the various components and
interconnections within an IC design.
[4]
- OASIS (Open Artwork System Interchange Standard) is a file format used in the
semiconductor industry for representing the layout of integrated circuits (ICs)
at the mask level. It is designed to address the limitations of the older GDSII
format and provide enhanced capabilities for handling larger and more complex
designs.
[5]
- LVS stands for Layout versus Schematic, which is a process commonly used in
the semiconductor industry for verifying the electrical connectivity
correctness of an integrated circuit (IC) layout with respect to its
corresponding schematic representation. The LVS process is crucial in ensuring
that the physical implementation of an IC accurately reflects its intended
circuit design. By verifying that the layout and schematic electrical
connectivity are consistent and matched, potential design errors, such as
missing or incorrectly connected components, can be detected and corrected
before manufacturing.
[6]
- DRC stands for Design Rule Checking, which is a crucial step in the design
and verification process of integrated circuits (ICs). DRC involves analyzing
the layout of an IC design to ensure that it complies with a set of predefined
design rules and manufacturing constraints. The purpose of DRC is to identify
potential layout errors and violations that could affect the functionality,
performance, or reliability of the IC during manufacturing or operation. These
design rules encompass various aspects of the layout, including spacing between
components, width and length of interconnects, overlap of layers, alignment of
structures, and other geometric constraints. By performing DRC, designers can
catch potential issues early in the design process, minimizing the risk of
costly errors and rework during fabrication. DRC helps ensure that the layout
adheres to the manufacturing process capabilities and constraints, improving
the manufacturability and yield of the IC.
[7]
- DFM stands for Design for Manufacturing, which is a methodology used in the
integrated circuit (IC) design process to optimize the manufacturability and
yield of ICs. DFM focuses on designing IC layouts that are compatible with the
capabilities and constraints of the semiconductor fabrication process. The goal
of DFM is to identify and address potential manufacturing issues early in the
design phase to minimize the risk of costly rework, yield loss, or performance
degradation. By considering manufacturing constraints during the design
process, DFM aims to improve the efficiency, reliability, and overall success
of IC manufacturing.
[8]
- HDL stands for Hardware Description Language, which is a specialized language
used in the design and verification of digital integrated circuits (ICs). HDLs
allow designers to describe the behavior, structure, and timing of digital
systems at various levels of abstraction.
About US
GBT Technologies,
Inc. (OTC PINK: GTCH) (“GBT”) (http://gbtti.com) is a
development stage company which considers itself a native of Internet of Things
(IoT), Artificial Intelligence (AI) and Enabled Mobile Technology Platforms
used to increase IC performance. GBT has assembled a team with extensive
technology ability and is building an intellectual property portfolio
consisting of many patents. GBT’s mission, to license technology and IP to
synergetic partners in the areas of hardware and software. Once commercialized,
it is GBT’s goal to have a suite of products including smart microchips, AI,
encryption, Blockchain, IC design, mobile security applications, database
management protocols, with tracking and supporting cloud software (without the
need for GPS). GBT envisions this system as a creation of a global mesh network
using advanced nodes and super performing new generation IC technology. The
core of the system will be its advanced microchip technology; technology that
can be installed on any mobile or fixed device worldwide. GBT’s vision is to
produce this system as a low cost, secure, private-mesh-network between all
enabled devices. Thus, providing shared processing, advanced mobile database
management and sharing while using these enhanced mobile features as an
alternative to traditional carrier services.
Forward-Looking Statements
Certain
statements contained in this press release may constitute "forward-looking
statements". Forward-looking statements provide current expectations of
future events based on certain assumptions and include any statement that does
not directly relate to any historical or current fact. Actual results may
differ materially from those indicated by such forward-looking statements
because of various important factors as disclosed in our filings with the
Securities and Exchange Commission located at their website ( http://www.sec.gov). In addition to
these factors, actual future performance, outcomes, and results may differ
materially because of more general factors including (without limitation)
general industry and market conditions and growth rates, economic conditions,
governmental and public policy changes, the Company’s ability to raise capital
on acceptable terms, if at all, the Company’s successful development of its
products and the integration into its existing products and the commercial
acceptance of the Company’s products. The forward-looking statements
included in this press release represent the Company's views as of the date of
this press release and these views could change. However, while the Company may
elect to update these forward-looking statements at some point in the future,
the Company specifically disclaims any obligation to do so. These
forward-looking statements should not be relied upon as representing the
Company's views as of any date subsequent
to the date of the press release.
Contact:
Mansour Khatib,
CEO
info@gbtti.com
*Functionality
information about those tools have been withheld on purpose and will be
disclosed when approved to protect the integrity of the IP.
**
Magic2 has been designed as an independent tool in mind. Each tool can be used
as a stand-alone version just loading the generic datafile much like you load a
CVS file into a spreadsheet. This generic data exchange protocol insures that Magic2
tools can be used in conjunction with all the current leading design packages
from Cadence, Synopsis, Siemens, Mentor Graphics enhancing the capabilities for
any company designing advanced semiconductors such as Apple, IBM, Intel,
Qualcomm, Samsung, TSMC, GlobalFoundries and more. The key advantage is that
you will be able to use this tool out of the box without interruption, long
learning curve or complicated software integration.
GBT Technologies Inc. (OTCQB:GTCH) is a
featured tech stock on Investorideas.com
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